I am still having trouble with premature overcurrent tripping> following my post and your answers from Sept 2025, I have increased the dead time from the " aggressive 100ns" to 1.1us I have also run for a short time with the LS device disabled, relying on its diode for flywheel duty. It still trips, so it definitely is not shoot through.

Background info. The circuit runs as a simple buck regulator with low side device acting as flywheel diode, now running at 30 kHz. the inductor is 100uH and air cored, just a coil of 35mm2 cable. The whole system is driving a flash lamp in pulse mode, i.e. it is intended to flash the lamp for typically 1 to 10 ms and 1 to 100Hz but with the mark space ratio of never more than 10%. Current 100 to 600A, supply 900v across a substantial capacitor bank.

I have attempted to measure the HS Vds again at the same time as the HS gate pulse. this was precarious! with the scope battery powered and floated to dc link voltage with voltage clamp to protect the standard scope probe used for the Vds and a differential probe for the gate. Not ideal as the diff probe leads are long separate wires. however I judged the Vds should be reasonably accurate and the timing from the beginning of the gate pulse to Vds coming below 2.9v is visible.

The yellow trace in volts, clamped at 5.1v, measuring down from HS drain, Blue is the gate voltage rising.at 5v/div. Gate resistors on the CGD1200HB2P-BM3 are all 1R. The Vds seems to come below 2.9v after about 1.6us even though these conditions did not trip. Obviously the noise and some measurement in accuracy muddies the water a bit but the general theme seems that the Vds stays around 3v and then starts to reduce after about 1.5us.

You mentioned in your answers to my previous post, that power loop inductance is a critical factor in system ringing. At these power levels I am not using a PCB, there are cables coming from the 900v capacitor bank, these run as a parallel pair as far as is practical but the capacitors are big and some inductance is unavoidable. I have a lot of capacitance across bus bars to the Power Mosfet pair, 100uF, a 50uf coupled as closely as possible with a further 2uF directly across the MOSFET terminals. I have looked at voltage here and the overshoot at when the HS switches off is very minimal bump. I have a Rowgowski probe but I cannot physically put it around the HS drain connection because the metalwork bus bars are so closely coupled, I imagine the high frequency ringing is coming from the local capacitors rather then the bigger power loop.

Photo of the layout below, the clamp for measuring the Vds is temporarily attached.

I am temped to increase the over current trip blanking time by increasing the value of value of CB9 and CB21 of the driver, currently 56pF, I have ordered some 100pF 0603 components in case. I note that you don't recommend this but question will the device really be damaged by an over current lasting say 2us?

Thank you in anticipation for any guidance, I can supply more detail if needed.

Ian