I noticed that in the file crd_22ad12n_design_files, the schematic of the auxiliary power supply board does not match the PCB layout. Some components that appear on the PCB, such as R534 and C457, are not shown in the schematic.

Could you please provide a correct and consistent set of drawings (including both the schematic and the PCB layout) for reference?

Thank you very much for your support.

Best regards,
Kevin

Hello, I hope you're doing well.

I wanted to ask if it is possible to obtain the Altium design files for the CRD-25BDA6512N-K 25 kW T-type reference design. The currently available PCB files are in PDF format, unlike other Wolfspeed reference designs that provide full design files.

I greatly appreciate if it can be provided. Thank you in advance!

I am currently working on CRD-06600FF065N-K eval kit can you pls confirm from your side weather below are the required software to run the kit pls confirm through the email provided and can you also pls share the detailed design calculations.

1.Cree GUI from wolfSpeed (we need access to run ECANTest.exe file which we got from vendor to access the GUI).

2.ECANTools software developed by vendor for WolfSpeed Eval Kit (CRD-06600FF065N).

3.Need to install the below provided Drivers by Vendor.

If possible, can you arrange a demo for the Kit to show how to power up and get the readings and collect the graphs. currently the kit is available with us
With regards,
Chakradhar
cb.en.p2ael24009@cb.students.amrita.edu

I just bought a CRD25DA12N-FMC and would like to exercise with lowest possible DC-link voltage to start with. Can you please let me know the lowest possible DC-link voltage I can use for my initial evaluation?

Thanks!

I'm working with CRD-03600AD065E-L reference design，but i found the firmware you provide not match the Schematics ，the firmware is 1ph3interleaved totem pole topology。Could you help me corrected？thank you.

I recently started working with the CRD250DA12E-XM3 inverter:

I would like to understand the dv/dt characteristics of this device better. Answers or pointers to the correct direction for the following questions would be much appreciated:

What are the different ways to alter the dv/dt of the device? From the existing datasheet, Vds and rise time, which are affected by the external gate resistance (is it by default that no external gate resistance is connected?) and junction temperature, both impact the dv/dt value. Are these all the factors that affect dv/dt?

How stable is the dv/dt under fixed conditions? How long does it take for the device to reach steady state? And is there a way to keep the dv/dt constant over a long period of time?

Many thanks.

If I simulate this in SPICE, these inductors seem to actually cause transients at the reciever input just from the normal switching of the transmitter. I'm sure the designer that chose 1uH and 27pF had good reason, just would like to know what those reasons were. Appreciate any insight on things like…

what type of noise are you trying to reject? inductive coupling? capacitive coupling?

what noise frequencies of interest?

were there concerns about crosstalk from other signals in the ribbon cable?

were there concerns about differential-mode noise? or mainly common-mode?

I'm not experienced with SiC designs at all, but my first thought is that the common-mode noise caused by the SiC MOSFET would be the biggest noise contributor on these differential lines. Why wasn't a traditional common-mode signal choke used instead, like a 0603USB-222MLC for example? Appreciate any insight you may provide.

Thank you,

Zackary Long

I'd like to use a single thermistor to read the temperature of my switching cell. I know it won't exactly reflect either junction temperature, but hoping it will at least sense the "general" area of the cell. If the SiC FETs are arranged in a side-by-side configuration like that shown in PRD-06752 (snipped below), then I would expect that both FETs are somewhat thermally coupled together to the switch-node. Since the high-side PSU is referenced to the switch node, would it make sense to power an isolated amp+thermistor circuit on that same PSU, and just attach the thermistor to the switch node? I will be using Wolfspeed SiC FETs which have the Kelvin-Source pin, so I think I would have to protect the iso amp's inputs from any dv/dt transients that might occur between Kelvin and Source pins. I will only sample temperature during "quiet" windows of the switching period. I'd greatly appreciate any feedback on this. Is this a bad idea?

Thanks!

Zackary Long

https://www.wolfspeed.com/tools-and-support/power/ltspice-and-plecs-models/

I linked the models to my latest PLECS version 4.9.8 . However any refence iam trying to run I get

"Error in component CRD200DA23N-GMA/Power Stage/FET1 while evaluating parameter Thermal description: File 'CAB5R0A23GM4' was not found in the search path"

I looked at the path and see the file names but looks like the thermal models are missing from wolfspeed download from above path ?

Please help to resolve asap

https://www.wolfspeed.com/tools-and-support/power/ltspice-and-plecs-models/

I linked the models to my latest PLECS version 4.9.8 . However any refence iam trying to run I get

"Error in component CRD200DA23N-GMA/Power Stage/FET1 while evaluating parameter Thermal description: File 'CAB5R0A23GM4' was not found in the search path"

I looked at the path and see the file names but looks like the thermal models are missing from wolfspeed download from above path ?

Please help to resolve asap

I am planning on purchasing a kit based on MOD-MB-3P-0900V-40A-N and I would like to use it with one of TI's control cards (see details of the kit in attached document). I understand that this motherboard support NXP card interface by I couldn't find the MOD-MB-3P-0900V-40A-T (mother board that supports TI control card interface) for purchase at any of the distributors.

The user manual for MOD-MB-3P-0900V-40A-X mentions that "Adapter boards may be available upon request from Wolfspeed to accommodate using either control board on a single motherboard ". The mother board in my case will be MOD-MB-3P-0900V-40A-N. Please provide detailed information on TI control cards that are compatible with MOD-MB-3P-0900V-40A-N (supports NXP card interface only) and the necessary adapter boards and the instructions to make the necessary connections with the selected TI control card.

Thank you!

Is there a standard inductor to use for L1-L3 for CRD25DA12N-FMC-AFE. The listed inductor in the BOM "SUNLORD ARCDC704772A301N1B" does not seem like a readily sourceable part.

Alternatively, does this design use a standard footprint so an alternative P/N could be used?

Thanks in advance!

There's a 5.1 k resistor in series and my plan is to put the Schottky diode

I have a research project that will utilize a new old stock Cree evaluation kit (CRD200DA12E). I was only given a document containing a few pages of overview of this evaluation kit.

Does anyone have the full documentation package for this evaluation kit? I'm especially interested in the gate drive circuit board and current & voltage sensor schematics.

Thanks!

djsubert

Per customer, “Is the SiC MOSFET half bridge module inverter (CRD-5FF0912P) working in 1MHz or switching frequency is 1MHz?? “

I have a question regarding the simulation model of the "C3M0900170J" MOSFET.

For my design, I would like to simulate the circuit with the C3M0900170J in SIMPLIS.
The reason is that other components of the circuit are only available in SIMPLIS.

Thus, I would like to know if the simulation model of the C3M0900170J can be made available for SIMPLIS.

Thanks in advance!

Best regards,

Thomas

This is regarding the CAN GUI software that is used to communicate with the CRD25DA12N-FMC 25 kW Three-Phase Inverter. I wish to deploy this same functionality in a User Interface I am designing myself. Therefore, I am requesting access to the CAN protocol library with a list of all the CAN messages and the data description. If possible, a DBC file would be great.

Thank you and best regards,

Mohammed Mahedi Hasan

I recently purchased and have been working with the CRD25DA12N-FMC 25 kW Three-Phase Inverter. I have a few questions regarding resolver compatibility and system protections, and I’d appreciate your guidance:

1. Excitation Signal Voltage:
   I measured the voltage magnitude at the EXC P and EXC N terminals as 15V. Can you confirm if this is the expected excitation signal level?
2. Resolver Compatibility:
   I plan to use the TE 2367237-1 resolver (Size 21, 3 pole-pair, hollow-shaft) with the following specs:
   • Excitation (input) voltage: 3 V (rms)
   • Typical frequency: 8 kHz
   • Max input current: 40 mA
     The current excitation signal appears incompatible with this resolver. Could you advise on how to modify either the software programming or hardware configuration (e.g., voltage reduction) to make it work with the J16 Resolver Connector?
3. Protections Implemented:
   Could you provide details on the hardware and software protections (e.g., overcurrent, overvoltage, thermal) integrated into the inverter board?

I’d greatly appreciate your prompt response to ensure seamless integration. Thank you for your support!

Best regards,

MT Faiz

I am currently designing a high-power DC-DC converter and utilizing your CAB400M12XM3 power modules along with the CGD12HBXMP gate drivers. I would like to request your guidance regarding the optimal DC bus bar and DC bulk capacitor layout.

Due to space limitations in my mechanical design, the area available for placing the DC bus bars and bulk capacitors is quite constrained. I understand that minimizing stray inductance is critical for proper switching behavior, especially in fast-switching systems like SiC modules.

Specifically, I would appreciate your input on the following:

• Are there any recommended example layouts or mechanical guidelines for DC bus bar placement in conjunction with the CAB400M12XM3 module?
• Do you recommend a vertical stack arrangement for the +DC and −DC bus bars to reduce loop inductance?
• What would be your best practices for placing DC bulk capacitors in this context, especially in tight mechanical arrangements?
• If available, could you kindly share any reference designs, application notes, or mechanical drawings that illustrate an optimized DC bus bar and capacitor configuration for this module/driver combination?

Any advice, examples, or visual documentation would be extremely helpful as we move forward with mechanical integration and layout optimization. Thank you very much in advance for your support and expertise.

Best regards,

Pederas

Fig.1

Fig.2

CAB5R0A23GM4, CAB6R0A23GM4 - for these power modules case isolation voltage(rms) is given in the datasheet as shown below. Can you please mention the VDC value for the same. Also, can you please suggest the max. operating frequency of these modules.

I am interested in DAB-related research projects and have reviewed your 60kW Dual Active Bridge (DAB) reference design. I would like to know the extent to which this design has been tested under real conditions.

I have experience working with a 15kW DAB converter, which was based on a 4-layer PCB design. However, I occasionally encountered noise issues in voltage measurements. Currently, I am using your Gen 3 half-bridge fet modules and gate driver modules in my design. I’m also particularly interested in gaining experience with the Gen 4 modules.

I have also downloaded the design files from your website and reviewed them thoroughly. Could you please confirm whether these are the most up-to-date versions or if a newer revision is available?

Lastly, do you provide a user guide or documentation for the 60kW design?

Thank you for your support.

Best

Sachith

I don't recall having this problem with older versions of LTSpice but when I try and run with wolfspeed model of C2M0045170D I get the following (see below). Any ideas ? Thanks Joe

C2M0045170D.lib(188): Expected ")" here.

• -drain_current(V(gk),V(s1,d3),V(NET3),gain(V(gk),V(Tjc)),nval(V(gk),V(Tjc)),lam3(V(gr),V(Tjc)),mod(cx(V(gk),V(Tjc)),kx(V(gk),V(Tjc)),V(s1,d3))))