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        <title>Hardware Design — Wolfspeed Power Applications Forum</title>
        <link>https://forum.wolfspeed.com/</link>
        <pubDate>Mon, 20 Apr 2026 06:16:24 +0000</pubDate>
        <language>en</language>
            <description>Hardware Design — Wolfspeed Power Applications Forum</description>
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        <title>[FAQ-HW-3] How can I control the Slew Rate of SiC MOSFET&#39;s</title>
        <link>https://forum.wolfspeed.com/discussion/55/faq-hw-3-how-can-i-control-the-slew-rate-of-sic-mosfet-039-s</link>
        <pubDate>Thu, 05 Aug 2021 19:55:38 +0000</pubDate>
        <category>Hardware Design</category>
        <dc:creator>SiC_Power_Admin</dc:creator>
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        <description><![CDATA[<p>The slew rate is easily controlled with an external gate resistor between the gate driver and SiC MOSFET gate. The higher the value of the resistor, the slower the slew rate will be, but the switching losses will increase. This is a design tradeoff between EMI (dv/dt) and switching losses.</p><p>It is important to note that the external gate resistor is only a portion of the total resistance in the gate path.    The schematic below shows all of the different components of gate resistance.  Rgext(on) and Rgext(off) in the schematic below are the external gate resistors. </p><div data-embedjson="{&quot;url&quot;:&quot;https:\/\/forum.wolfspeed.com\/uploads\/WAP2STF3EPCA\/image.png&quot;,&quot;name&quot;:&quot;Gate Resistance.png&quot;,&quot;type&quot;:&quot;image\/png&quot;,&quot;size&quot;:6684,&quot;width&quot;:305,&quot;height&quot;:129,&quot;displaySize&quot;:&quot;medium&quot;,&quot;float&quot;:&quot;none&quot;,&quot;embedType&quot;:&quot;image&quot;}">
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            <img src="https://forum.wolfspeed.com/uploads/WAP2STF3EPCA/image.png" alt="Gate Resistance.png" height="129" width="305" data-display-size="medium" data-float="none" data-type="image/png" data-embed-type="image" /></a>
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    <item>
        <title>[FAQ-HW-2] Do I need to add short circuit protection ? Is it different from IGBT Desat protection ?</title>
        <link>https://forum.wolfspeed.com/discussion/54/faq-hw-2-do-i-need-to-add-short-circuit-protection-is-it-different-from-igbt-desat-protection</link>
        <pubDate>Thu, 05 Aug 2021 19:29:02 +0000</pubDate>
        <category>Hardware Design</category>
        <dc:creator>SiC_Power_Admin</dc:creator>
        <guid isPermaLink="false">54@/discussions</guid>
        <description><![CDATA[<p>The need for short-circuit protection depends on the application and reliability requirements.  </p><p>SiC MOSFETs are capable of withstanding several microseconds of short circuit conditions (MOSFET gated on with minimal resistance or inductance to limit the rate of current rise) where the drain current rises very quickly. However, in order to prevent damage to the MOSFET, the fault condition must be detected and the MOSFET turned off quickly.  </p><p>Although SiC MOSFETs do not exhibit desaturation behavior like IGBTs, the voltage across the drain to source of the part will increase as the current increases. Therefore, a circuit very similar to an IGBT desat circuit can be used to detect the fault condition. The exact voltage levels and timing requirements are different for SiC MOSFETs. We have worked closely with our gate driver partners at Analog Devices, Silicon Labs, Texas Instruments, NXP, and Broadcom to develop robust short-circuit protection solutions. </p><p>A report for short-circuit testing with one our 1200V MOSFET's is available <a href="https://forum.wolfspeed.com/home/leaving?allowTrusted=1&amp;target=https%3A%2F%2Fcms.wolfspeed.com%2Fapp%2Fuploads%2F2021%2F05%2Fdriving_cree_c3m_sic_mosfets_with_silicon_labs_si828x_gate_drivers_in_applications_requiring_short_circuit_protection.pdf" rel="nofollow noopener ugc">here</a>.</p>]]>
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    <item>
        <title>[FAQ-HW-1] Are there any special considerations for PCB layout when designing with SiC ?</title>
        <link>https://forum.wolfspeed.com/discussion/48/faq-hw-1-are-there-any-special-considerations-for-pcb-layout-when-designing-with-sic</link>
        <pubDate>Thu, 05 Aug 2021 14:01:00 +0000</pubDate>
        <category>Hardware Design</category>
        <dc:creator>SiC_Power_Admin</dc:creator>
        <guid isPermaLink="false">48@/discussions</guid>
        <description><![CDATA[<p>Careful design is needed for PCB layout when using SiC MOSFETs (similar to Si MOSFET designs) in switching power supplies. Some best practices are listed below:</p><p>	• Minimize the loop inductance of gate drive circuit</p><p>	• Use the shortest leads possible for through-hole devices to minimize parasitic inductance</p><p>	• Avoid overlapping of gate and drain traces to minimize Cgd and cross talk in hard switching bridge  circuits</p><p>	• Minimize common source inductance to prevent slowing down gate drive and gate oscillation for 3-lead devices. This can be done by making a kelvin connection where the device terminal meets the board. The gate drive circuit should connect to the source lead separately from the power path, and the gate drive circuit should not overlap the power circuit. Packages with kelvin source connections for the gate drive make it easier to separate these circuits on the PCB, and also improves switching speed.  </p><p>	• Use low inductance DC bus configurations. Using high quality film and/or ceramic capacitors placed as closely to the devices as possible will help to reduce ringing and voltage overshoot at turn-off. The DC bus should use overlapping pours in a PCB or laminated bus structures when working with modules.  </p>]]>
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        <title>[FAQ-HW-3] Can discrete SiC MOSFET&#39;s be placed in parelell for higher currents ?</title>
        <link>https://forum.wolfspeed.com/discussion/47/faq-hw-3-can-discrete-sic-mosfet-039-s-be-placed-in-parelell-for-higher-currents</link>
        <pubDate>Thu, 05 Aug 2021 14:01:00 +0000</pubDate>
        <category>Hardware Design</category>
        <dc:creator>SiC_Power_Admin</dc:creator>
        <guid isPermaLink="false">47@/discussions</guid>
        <description><![CDATA[<p>Yes, SiC MOSFETs can be operated in parallel much like a Si MOSFET. However, the layout is more critical due to the faster switching times on SiC devices. Maintaing symmetry in both the gate drive and power loops is one of the most important factors in good dynamic sharing.</p>]]>
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