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Capacitor in parallel between GATE-SOURCE

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Alan_Arag
Alan_Arag Contributor Level 1
edited July 30 in Discrete Products

Hello, Wolfspeed experts!

I have some questions regarding some application notes I've been reading ("PCB LAYOUT TECHNIQUES FOR DISCRETE SiC MOSFETs" [1] and "CAPACITANCE RATIO AND PARASITIC TURN-ON" [2]).

In section 2.3.1 Compact Gate Loop [1], they mention that a capacitor in parallel between the MOSFET's GATE-SOURCE is recommended, but exclusively for packages with a KS pin.
Reading the following application note [2], in section 4. Other factors that influence parasitic turn-on -> gate capacitance: if an external CGS is added, the equivalent CGS would be higher (artificially increasing the capacitance ratio) and hence the gate voltage increase (𝑑𝑣𝐺𝑆) would be lower. As long as the time it takes for VDS to switch (dv/dt time) is much smaller than the time constant due to gate resistance and capacitance forming an RC circuit.
My question is: Why is such a capacitor between G-S not recommended in a 3-pin MOFSET (TO-247-3)?
Wouldn't it help reduce the Vpeak of the MOSFET's G-S?

In addition to the above, we could say that Cgs = Ciss and Cds = Crss?

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  • Forum_Moderator
    Forum_Moderator Wolfspeed Employee - Contributor Level 5
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    Thank you for your post, it has been approved and we will respond as soon as possible.

  • TBhatia
    TBhatia Wolfspeed Admin - Contributor Level 5
    edited July 30
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    Hello Alan,

    For the 3L MOSFETs, the source inductance Ls (device + PCB) is part of the gate drive loop. The Ls contribution of the PCB most times is in the range of 5-20nH. The addition of an external Cgs creates a RLC resonant circuit with the internal Rg and this Ls shown in the figure below:

    image.png

    This resonant circuit can contribute to oscillations (sometimes even sustained oscillations) from the gate to source depending on the switching speed and the value of Ls. You can see the effect of increasing Ls with a 1nF external Cgs below on the gate oscillations (in red).

    image.png

    I recommend using MOSFET packages with a kelvin source pin as it isolates the gate loop from the power loop. Minimizing your overall loop inductance is very critical if you're using 3L MOSFETs.

    Also,

    Ciss= Cgs + Cgd

    Crss= Cgd

    Coss= Cgd + Cds

  • Alan_Arag
    Alan_Arag Contributor Level 1
    edited July 30
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    Thank you very much for your response and attention.

    Now I understand better.

This discussion has been closed.