premature overcurrent tripping of gate driver CGD1200HB2P-BM3

ianp

I am having some trouble with a switching power supply which uses Si Ca MOSFET switch pair CAB530M12BM3 and a gate driver CGD1200HB2P-BM3 driver driven by a CGD12HB00D transceiver.

The problem is that if I try to increase the current much beyond about 300A, the driver will trip on over current. This current is no where near the level that should cause a trip. I am looking for reliable running at 600A.

My question concerns the gate driver gate driver CGD1200HB2P-BM3. How much time is allowed after sending the gate voltage high, before the drain source voltage limit of 2.9 volts is activated?

It surely takes time for the Si Ca MOSFET to switch on and the drain source voltage to come down.

There doesn’t seem to be any mention of this time in the data sheet for the driver other than the over current blanking time of 0.5 to 2us. Is this the time that I am referring to? If so it seems very short, in our case it takes longer for the voltage to settle below the threshold.

Oscilloscope trace below shows the Drain Source voltage of the high side device while running at about 320A. the voltage is measured down from the Drain (+ve dc rail) (the scope probe is protected by 100k resistance and 5v1 zener, hence the -5v limit).

The DS voltage does falls to a bit less than a volt but seems to take about 2.5us to get below 2v.

The gate drive resistors are unchanged at 1R, however the Zener diodes DB2 and DB10 have been changed from 5v1 to 3v9 to give a 1.2v increase D-S trip voltage from 2.9v to 4.1 v. This was done in an attempt (unsuccessful) to fix the over current trip problem. The trace shows some ringing as the D-S voltage comes down, is this normal?

Background info. The circuit runs as a simple buck regulator with low side device acting as flywheel diode, running at 50 kHz, the control circuit is based on a current mode control chip UC3843, the high side and low side devices are driven in anti-phase with dead times (anti overlap) of at least 100ns, these are generated in my control circuit. The whole system is driving a flash lamp in pulse mode, i.e. it is intended to flash the lamp for typically 1 to 10 ms and 1 to 100Hz but with the mark space ratio of never more than 10%. Current 100 to 600A, supply 900v across a substantial capacitor bank. The output (lamp) pulses are switched on and off using the PWM-En control, the PWM runs continuously.

I look forward receiving any guidance on this.

Ianp

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