SpeedFit™ Design Simulator
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Start a SimulationHS & LS bias in CDG1700HB2P-XM3
Hello:
Can some one explain how HS_VDD and LS_VDD all are 5V in CDG1700HB2P-XM3?
Should they not be of gate drive capable voltages tied to the respective halfbridge nodes?
Furthermore, in some other App note on Gate Driver board, the bias levels developed are +25V and -5V
In the App Note in discussion here, there is nowhere any such bias voltages one can see.
One more thing: In the App Note where 25V is generated, one cannot locate how that can be applied to any TI or any other gate driver VDD pins. They are all restricted to 18V . Some, maybe to 22V.
Appreciate clarification of these issues.
-robin
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