CAB006M12GM3 gate driver layout in parallel and NTC connections

jiten000

We are designing 2 level Active Front End with CAB006M12GM3. 2 modules per phase are connected in parallel.

• As per application note PRD-08911, Section 5.2 Power Layout Design, gate loops and power loops should not overlap. Is it ok to overlap gate drive loop of high side with DC planes. As DC plane voltages are constant, so dV/dt is negligible and hence capacitive coupling should not create issue? Does high dI/dt magnetic coupling create problem for gate drive?
• Single driver with isolated analog sensing is selected to drive paralleled modules, is it ok connect NTC of 1 module to high side gate driver and NTC of another paralleled module to low side gate driver? Will it create problem for isolation or noise?

Regards,

Jitendra

Forum_Moderator

Thank you for your post, it has been approved and we will respond as soon as possible.

ChrisN

Hello Jitendra,

As discussed in the indicated section of the PRD-08911, the ideal layout would be to have no overlap between the gate and power loops. However, in practice — when dealing with application-specific constraints — we recognize that this is not always achievable. In these cases, we still recommend limiting noise coupling through two primary methods: (1) route the gate signals over the DC planes instead of the AC terminals, and (2) route the gate signals perpendicular to the flow of current in the power planes. In your case, routing the gate signals over the DC planes should be fine. You should still follow best practices for gate driver design, when possible. Having long connections — and therefore high inductance — between the power module and the gate driver can result in undesirable dynamics, regardless of whether you have high coupling between the gate and power loops. PRD-09311 provides more information on best practices for gate driver design for SiC power modules.

The NTC sensor in the power module is isolated from the other voltages. However, in the unlikely case of a catastrophic failure in the module, a wire bond or other debris may bypass this isolation barrier to the NTC sensor. For this reason, Wolfspeed recommends having an additional isolation barrier for the NTC feedback measurement (which it sounds like you are already adopting through the use of the gate driver with isolated analog sensing). It should not be a problem connecting the different NTCs to the high and low side gate drivers. The time constant of an NTC measurement is very long compared to all the electrical signals, so the signal can be aggressively filtered without loss of information. It is noted that in some Wolfspeed documentation, you may see that Wolfspeed typically recommends attaching the NTC to the low-side gate driver. This recommendation is based on situations where the NTC feedback could be routed to either the high or low side positions, in which case you might get minor noise improvement due to the better reference voltage. However, in all these cases and in your design, the high-side switch position is still sufficient. Section 3.4 of PRD-09311 provides some additional guidance on NTC feedback in SiC gate drivers.

Thanks,

Chris N.