[FAQ-PCB-2] Are there any special considerations for PCB layout when using SiC MOSFETs?

TBhatia

Care is needed for PCB layout when using SiC MOSFETs just like using Si MOSFETs in switching power supplies. Some best practices are listed below:

• Minimize the loop inductance of gate drive circuit

• Use the shortest leads possible for through-hole devices to minimize parasitic inductance

• Avoid overlapping of gate and drain traces to minimize Cgd and cross talk in hard switching bridge circuits

• Minimize common source inductance to prevent slowing down gate drive and gate oscillation for 3-lead devices. This can be done by making a kelvin connection where the device terminal meets the board. The gate drive circuit should connect to the source lead separately from the power path, and the gate drive circuit should not overlap the power circuit. Packages with kelvin source connections for the gate drive make it easier to separate these circuits on the PCB, and also improves switching speed.  

• Use low inductance DC bus configurations. Using high quality film and/or ceramic capacitors placed as closely to the devices as possible will help to reduce ringing and voltage overshoot at turn-off. The DC bus should use overlapping pours in a PCB or laminated bus structures when working with modules.  

Please refer to the full Application note PCB LAYOUT TECHNIQUES FOR DISCRETE SiC MOSFETs for detailed design considerations and tips for a good layout using discrete SiC MOSFETs.