gate-source voltage oscillation when paralleling two C2M0025120D

Musk

Hello , 

Now we test a three phase inverter using C2M0025120D, fs=10kHz, each place has two SiC MOS in parallel, totally 12 SiC MOSFETs, performing Double pulse test.

However, when DC voltage and current increase, both SiC MOSFET gate-source voltage start to oscillate at the miller pleteau, sometimes the oscillation even cause failure as shown below.

yellow line: upper leg Vgs  green line: lower leg Vgs  blue line: upper Vds  red line: upper Ids

At DC voltage=400V / Ids=20A ,we replace all C2M0025120D with C3M0015065D, under same PCB and test condition, the gate-source oscillation disappear. I'm wondering what difference leads to this phenomenon?

Our parallel MOSFET both use individual turn-on/turn-off resistance, which is 4.7ohm. 

We place a 1000pF and 10kohm between each MOS gate-source. From each parallel MOS source to driver IC, we connect an 1ohm in series. Each MOSFET drian-source Cds we put a 2000pF cap in parallel. 

My question is： 1. Can you give some suggestion about how to reduce the gate-source turn-on oscillation when parallel SIC MOSFETs?(except for change PCB layout)

2 What difference between C2M0025120D and C3M0015065D leads to different gate-source oscillation phenomenon under the same condition?

Thank you, looking forward to your response.

Forum_Moderator

Thank you for your post, it has been approved and we will respond as soon as possible.

AAnders

Hello,

Thank you for your question. Let me start by saying that the C2M0025120D is not recommended for new designs. Depending on your requirements, the C3M0021120D or C3M0032120D would be preferred alternatives using our current Gen 3 technology. Please note that when switching from 2nd to 3rd generation the gate voltage requirement changes from +20/-5 to +15/-3 to -4. The reason you may be seeing a difference in the behavior between the two parts that you are testing is that the 2nd generation body diode tends to have more ringing, so as the upper device turns on and the lower device is going into reverse recovery it can introduce oscillations into the circuit.

Some things that you can try to improve the situation is:

1. Remove Cgs - on 3-terminal MOSFETs, this can actually introduce additional gate oscillations because of the common source inductance in both the gate and power loops.
2. Remove Cds - this is generally not needed and again may introduce oscillations. If this is needed to help with voltage overshoot, consider adding a series resistor to help damp any oscillations.
3. Add a ferrite bead in series with each device gate. This can help attenuate the high frequency ringing without significantly impacting switching losses
4. It sounds like you may already have this, but just to be sure, each MOSFET should have its own gate resistor as shown in the diagram below to prevent current from circulating between the two device gates.

In the future if you do make PCB changes, here are some recommendations to improve performance when paralleling.

1. Use devices with a kelvin source (TO-247-4, TO263-7, etc)
2. Ensure symmetry in both the gate and power loop for each device
3. Avoid any overlap between the switching node and the gate loop. All gate circuitry should have a kelvin source pour on an inner layer and not overlap the drain at all.
4. Add a small amount of parasitic inductance in the power path of each device. Ensure that it is the same for both devices. This helps balance any asymmetry in turn-on and turn-off due to parameter variation between the devices.

Please let us know if you have any additional questions, or if you have any new information after testing the suggestions above.

Thanks,

Adam

TBhatia

Hi, I hope that this answered your question. I will close this discussion for now but if you have a follow up question, please "Start a New Discussion" and we would be glad to support you further.