crd_06600ff065n_k firmware about SR

Abby

Hi, Team:

there are some firmware code that i could not understand in the [BAT_Isr.c] file of crd_06600ff065n_k reference design.

As listed below,There are five parameters in the formula, but can you please explain What principle are they based on? and how to calculate the parameters?

IsrVars.f32SRDelay = __fsat(
-0.6128fIsrVars.f32Vin_Vo - 0.3377fIsrVars.f32Vin + 1650.0f

+ 0.4805fADC_BATCURR_DC_S

- 3.06f*((float32)IsrVars._lDcdcPWMTsShadow.iData.iHD),

700.0f, 350.0f);

Best Regards!

Forum_Moderator

Thank you for your post, it has been approved and we will respond as soon as possible.

Hzz

Hello,

This formula is basically used to calculate the rising edge timing of the SR(synchronous rectification) switches, the variable IsrVars.f32Vin_Vo equals to (Input voltage* Turns ratio of transformer)- output voltage, so this variable actually reflects the Gain of LLC tank. IsrVars.f32Vin corresponds to Input voltage, ADC_BATCURR_DC is the ADC value of output current on secondary side, IsrVars._lDcdcPWMTsShadow.iData.iHD corresponds to switching frequency.To get the optimal timing at the rising and falling edge of SR gate drive, the constant/coefficient before each variable need to be tuned step by step in accordance with the practical measured waveforms(SR gate signals, SR current) under each operating condition, there is no theoretical calculation in advance.

Thank you.

Abby

Thank for your reply.
   Another question in the [BAT_Isr.c] file of this reference design.what the theoretical
calculation of ePLL.f32Theta? how to calculate 44.0f and 41.0f? 
   The reference code listed below.
ePLL.i16Vac_ADC = ((int16)ADC_VACIN - 2100);

ePLL.f32Verr =  ((float32)ePLL.i16Vac_ADC)/4.242f - ePLL.f32Vamp_Est * ePLL.f32Sin_Theta;

ePLL.f32Vamp_Est += 0.00001f * 44.0f * ePLL.f32Verr * ePLL.f32Sin_Theta;

ePLL.f32deltaW_Est = __fsat(0.00001f * 41.0f * ePLL.f32Verr * ePLL.f32Cos_Theta

	+ ePLL.f32deltaW_Est, 10.0f*PI_2_VALUE, -10.0f*PI_2_VALUE);

ePLL.f32Theta += 0.00001f * ( 55.0f*PI_2_VALUE + ePLL.f32deltaW_Est + \

	0.74f * ePLL.f32Verr * ePLL.f32Cos_Theta );

THANK YOU!

TBhatia

Hello Abby,

At this time we're unable to support any more questions on the firmware of the design CRD_06600FF065N_K as the engineer who developed this firmware is not with Wolfspeed anymore.

You can refer to other online resources about firmware development and coding. We're happy to answer any other questions related to this design. Thank you!

TBhatia

Hi, I hope that this answered your question. I will close this discussion for now but if you have a follow up question, please "Start a New Discussion" and we would be glad to support you further.