Do I Need a Turn Off Gate Resistor?

Sean_HV

We are using C3M0015065K and we have noticed improvement to our thermals as we lower our turn-off gate resistor (we are using a gate driver with separate source and sink outputs). I would like to try going to 0 ohms in our turn-off path, leaving us with just the impedance of the gate driver (<0.5 ohms) and the FET, but we are concerned that there may be some reason why we shouldn't do this, as there is always shown to be some gate resistor used in this particular application, and the FET datasheet does not show performance for less than 2 ohms of gate resistance. Is there anything apart from overshoot we would have to worry about?

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TBhatia

Hello Sean_HV,

The external gate resistor of the MOSFET controls the switching speed. The improvement in thermals you're seeing is likely due to the decrease in switching loss (increase in switching speed) with lower Rg (gate resistor) values.

However, looking at the waveforms of the MOSFET the gate-source voltage and drain-source voltage is extremely critical for picking out the right Rg. The Vds and Vgs overshoot should be less than the maximum ratings of the MOSFET which are 650V and -8/+19V respectively for C3M0015065K. Measuring these signals correctly is critical so be sure to use high bandwidth scope and probes (>500MHz) and high CMRR (100MHz> 80db for Vgs and 100MHz> 26db for Vds) probes. If there is excessive ringing on the Vgs and Vds waveforms, you can try to increase your Rg or improve the PCB loop inductance of the Power loop (Vds overshoot/ringing), Gate loop (Vgs overshoot/ringing).

The dv/dt of Vds(off) is generally higher than dv/dt Vds(on) therefore choosing the right turn-off resistor is important. The Vds dv/dt should be taken care of for two main reasons:

• A good rule of thumb for the maximum dv/dt of SiC MOSFETs is 100V/ns to prevent the false turn-on of the parasitic BJT of the SiC MOSFETs. You want to make sure your dv/dt off is not greater than >100V/ns.
• Fast edges generate more noise and can lead to higher Electromagnetic Interference (EMI). However the EMI spectrum of the system needs to be measured to see if it compliant with whatever EMI compliance you're following to make a decision for lowering the switching speed (Increasing the Rg) of the MOSFETs.

At the end of the day, the PCB layout plays a huge role in taking care of the tradeoffs between getting faster switching speeds and generating more noise. You can refer to this application note for good practices on PCB layout: PCB LAYOUT TECHNIQUES FOR DISCRETE SiC MOSFETs

Let me know if you have any other questions. Thank you!

TBhatia

Hi, I hope that this answered your question. I will close this discussion for now but if you have a follow up question, please "Start a New Discussion" and we would be glad to support you further.