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I am using CAB450M12XM3 for my inverter design. I have connected it with a 3 phase inductive load. I have applied a duty ratio of 48 us to all the top switches and 48 us to all the bottom switches with 2 us dead time. So it is like no load scenario for the inverter. But when the top switch is turning OFF, its antiparallel body diode is turning on during the dead time. Only when the bottom switch is commanded on then only the top switch body diode stops conducting which is causing a brief shoot through issue.
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Hello Aradhya,
It is normal to experience switching loss even under no-load conditions as the output capacitance of the MOSFETs will charge and discharge when switching states. This phenomenon is actually utilized to discharge the DC link capacitor in some EV traction applications and is known as Active Discharge. I've attached a paper that explains the no-load loss mechanism.
Best Regards,
Austin C.
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Thank you for the response.
But here I am not worried about the switching losses. If you see the results, it is clear that when the mosfet is turned off, its body diode starts conducting during the dead time. This is strange for me. I am not able to understand the valid reason. I need input on this. Please suggest.
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Aradhya,
The current that you're observing in your simulation is not flowing through the body diode. This current is caused by the output capacitance of the device and is governed by i = C*dv/dt. You are creating a fast change in voltage across each MOSFET position (dv/dt), and the MOSFETs have an output capacitance (COSS), which causes a current to flow. I've added labels to your simulation result below:
The paper in the post above walks through this phenomenon in more detail, but here's an excerpt showing the current path for high-side turn-on (a, c) and low-side turn-on (b, d). This paper is identical to your simulation where you're switching between the two zero states of SVM (switching between all high-side on and all low-side on simultaneously).
Best Regards,
Austin C.
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The above phenomena is happening after the dead time. But please observe the waveform during the deadtime. It can be observed that there is an increase in switch node voltage. The switch node voltage was equal to the DC link voltage when the lower device is OFF and upper device is ON. When the upper switch turns OFF, the switch node voltage is rising. I am concerned for that aspect. My query is also related to that. I am worried about the phenomena that is occurring during the dead time not after that.
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Hi Aradhya,
Thank you for the clarification; I'm following your question now. Can you please clarify the voltage setpoints for V2, V3, V4, V5, V6, and V7? Is the off-state voltage 0 V or -4 V for VGS?
Best Regards,
Austin C.
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Hi Austin,
Thank you for understanding my query.The Gate voltage is 15 V during ON state and - 4 V during OFF state. It is same for all the switches.
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