CAB004M12GM4 Clarification
Hello, I see in the datasheet that there are two gate connections for the high and low side FETs. It is not clear if there is an internal connection for the pairs. Is there a preferred pair to use or must both sets be connected to the gate driver?
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Hello dpalombo,
The gate connections are internally connected. For best performance, it is recommended to use both pairs with a symmetrical layout to each. This configuration will provide the lowest inductance. If both pin pairs cannot be used, it is acceptable to run just one pin pair. In this configuration, there is not a recommended pin pair to use; either pin pair will provide the same performance. More details about this are discussed in Section 3.11 of PRD-09301.
Thanks,
Chris N.
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