Regarding the issue of maximum gate voltage

ponfus

Hello Wolfspeed Team,

I noticed that the datasheet of the 1200 V C3M series SiC MOSFETs specifies:

VGS(max) = -8 V / +19 V

and additionally states:

When using MOSFET Body Diode: VGS = -4 V / +19 V

I would appreciate clarification on the following questions:

1. In a normal half-bridge application, the body diode conducts during the dead time. If dv/dt-induced crosstalk, common-source inductance, or other parasitic effects cause the instantaneous gate voltage to drop below -4 V (for example, -5 V) during body diode conduction, does this violate the datasheet limitation?
2. Why is the allowable negative gate voltage reduced from -8 V to -4 V when the body diode is conducting? Is this related to gate oxide reliability, threshold voltage shift, interface traps, bipolar degradation, or another mechanism?
3. I noticed that a similar requirement does not appear in the datasheets of the 1200 V C4M/C4MS series devices. Does this mean that Gen4 devices no longer have this concern, or does the same limitation still apply but is no longer explicitly stated?

Thank you for your support and clarification.

Forum_Moderator

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