Cds Capacitance for ZVS Calculations

yfahmy

Hello,

I am interested in the drain source capacitance and the charge that will be moved onto and off of it during soft switching (ZVS). The data sheet for the 32120K and similar TO package FETs list Coss and Crss, which are typically subtracted to give Cds. One part I did not fully understand is the Vac of 25mV (applied to Vgs? Vds?). Does this imply this is a small signal capacitance and therefore cannot be used for the full Vds bus swing?

Or can I use the values provided so that at an 800V bus we should expect Cds ~= 100pF (fig 17) and therefore if softswitching is achieved in a two level converter that Qds ~= 80nC will be moved every switching cycle?

If it is indeed a small signal value is there a large signal value that can be provided by Wolfspeed? Or will this have to be measured in a test setup?

Thank you in advance.

Forum_Moderator

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yfahmy

Hi just wanted to ask about this again.

Thanks.

YuequanHu

·       Vac of 25mV is applied to Vds with Vgs = 0V when we do the measurement of output capacitance.

·       It is not just small signal capacitance, although a small signal AC voltage perturbation between drain and source is applied to measure capacitance. Please bear in mind we also have a DC voltage applied on top of the AC excitation signal.

·      Simply using Q = CV is not correct to calculate the stored charge since the capacitance changes with voltages. The correct way is to sum up all the charges accumulated when the device capacitor is charged from 0V to the target drain-source voltage, for example, 800V. Incorrect calculation: Q(0V to 800V) = C(800V) x 800V = 130pF x 800V = 104nC. Correct way: Q(0V to 800V) = sum (Cv*Delta V) = 200nC. Please see the attached file for more detailed explanation and calculations.

Apps_forum_ques_Shashank.docx

Let us know if this answers your questions.

yfahmy

Thank you for your response!

Your explanation makes sense and addresses my questions.

One follow up relates to the effects of different variables on Cds; the operating point is always changing but even a general idea would be helpful. Other than Vds, which factors, if any, will have the largest effect on Cds (Vgs, Fsw etc.)? Is there a good paper/textbook/resource you can recommend to learn about these effects?

I appreciate your expertise.

YuequanHu

Think about the depletion region near the drain when VDS increases. As VDS increases the depletion width increases and therefore the capacitance will decrease (C = V/d). The drain voltage has implication on the underlying semiconductor and will change capacitance.

Vgs shouldn't impact Cds much, but die size(active area), drift doping, Vds are the main factors.

Hope this helps.